This application is related to U.S. Patent Application No. 170,399, entitled Context Switching Method and Apparatus for Use in a Vector Processing System, by D. Bhandarkar et al.; U.S. Pat. No. 4,949,250, entitled Method and Apparatus for Executing Instructions for a Vector Processing System, by D. Bhandarkar et al.; and U.S. Patent Application No. 170,367, entitled Method and Apparatus for Handling Asynchronous Memory Management Exceptions by a Vector Processor, by F. McKeen et al., which are herein incorporated by reference.
The invention relates to data processing systems with vector processing generally, and specifically to such data processing systems which must react to arithmetic exception conditions during vector processing operations.
Certain high performance data processing systems include, in addition to a main or scalar processor, a separate vector processor to process vector instructions quickly and efficiently. Vector instructions direct a processor to perform memory, arithmetic or logical operations on data represented as vectors. The main or "scalar" processor processes the other instructions, which are often called scalar instructions. For example, scalar instructions direct a processor to perform memory, arithmetic or logical operations on logical and scalar data.
Vector processors are often designed to operate simultaneously with a scalar processor. During such simultaneous processing, problems may occur in the vector processor which may have an unfortunate impact on the scalar processor. For example, arithmetic exceptions, such as arithmetic overflow or underflow, may occur during a vector processor arithmetic operation. Actions taken in response to these exceptions can have a significant impact on the rest of the data processing system. For example, if such actions include interrupting the scalar processor, then the efficiency of the scalar processor declines. If, instead, the system prohibits the processing of subsequent instructions by the scalar and vector processors until the conditions are treated, then the efficiency of the entire system suffers.
In the IBM System/3090 VF, vector instructions are executed sequentially (i.e., one-at-a-time), and any exceptions encountered during execution of the instructions are recognized sequentially. In this system exceptions include exponent overflow, exponent underflow, fixed-point overflow, floating-point divide by zero and an unnormalized operand. When one of these arithmetic exceptions is recognized during the execution of an interruptible vector instruction (i.e., one which consists of multiple units of operation with interruptions being permitted between these units of operation), a nonzero exception-extension code is generated. That code indicates whether the interruption was due to a noninterruptible scalar instruction or an interruptible vector instruction, whether the result, if any, was placed in a scalar or vector register, and the address of the register.
As explained above, generating interrupts for vector processing arithmetic exceptions can cause problems for the operation of the scalar processor. This problem is exacerbated in the multi-tasking environment because the scalar processor might be executing instructions for an operating system function when it is interrupted by the vector processor which encountered an exception while executing an instruction for a user process.
An obvious solution to this problem is to prevent processing of operating system functions until all vector instructions from a user process are complete. This solution, however, reduces the efficiency of the data processing system.
Another solution is to prevent simultaneous processing of vector and scalar instructions. This drastic solution, however, defeats many of the advantages created through the use of a separate vector processor.
Data processing systems that perform multi-tasking (i.e., operate several different tasks or processes) require special handling of vector registers. For example, the IBM 3090 provides multi-tasking and the CPU divides its attention between a plurality of processes. Each process is executed for a short period of time before it is switched out of main memory and another process is brought in. The switching out process is termed a context switch. Every time a process is switched out, the current state or context of the machine is saved and the state of the next process to be switched in is restored. State information includes such elements as flags, status words, scalar registers, and vector registers.
The IBM 3090 uses write flags to avoid switching out every vector register every time a context switch occurs. Whenever a vector register is written to during the execution of a process, a corresponding write flag is set. When the current process is switched out, only the contents of those vector registers that were updated during the execution of the process are saved. This reduces system load by requiring the operating system only to save the contents of registers that have changed since the last save. The reduction in system load is accomplished at the expense of added hardware. Furthermore, the load on the system is still significant, however, because at every context switch the operating system must still save the contents of all vector registers that have changed, and the operating system must still restore the contents of the registers to prepare for the next process.
Since typical vector processors contain 8 to 16 vector registers with 32 to 128 elements per register, the saving of an old state and the restoring of a new state at every context switch creates significant overhead, especially when a large number of processes are sharing the processor, but only a few processes use vector instructions.